The present invention relates to flip-flops and in particular to D-type flip-flops which are suitable for particularly high clock rates.
The specialist publication “A Low-Swing Clock Double Edge Triggered Flip-Flop,” IEEE, Journal of Solid-State Circuits, Vol. 37, No. 5, May 2002, discloses a flip-flop having reduced power consumption in comparison with conventional flip-flops. In particular, unnecessary transitions of internal nodes are avoided to reduce power consumption. In addition, a trigger operation is used both for the rising and for the falling clock edges, so that the clock frequency may be reduced in comparison with single-edge triggered flip-flops.
US patent publication US 2004/0114702 A1 discloses a phase detector having a first flip-flop for sampling an incoming signal in accordance with a first local clock signal to generate a first sampled data signal, a second flip-flop for sampling the incoming data signal in accordance with a second local clock signal to generate a second sampled data signal, and a third flip-flop for sampling the second sampled data signal, on the basis of the first sampled data signal, to generate a binary control signal. The third flip-flop comprises a double-edge triggered flip-flop.
U.S. Pat. No. 5,250,858 discloses a double-edge triggered memory device, wherein the output signal is updated both at the rising and the falling edges of a clock input signal.
U.S. Pat. No. 6,300,809 B1 discloses a double-edge flip-flop providing two data transitions per clock cycle. In particular, a delayed version of the clock signal is provided in addition to the clock. In addition, two transparent latches comprising clock inputs are provided which are controlled by opposite polarities of the delayed clock signal. Finally, a multiplexer is provided, the inputs of which are fed by output signals of the latches, a select input of the multiplexer being fed by the clock signal. Moreover, a select signal is provided for selecting that latch whose clock is inactive.
U.S. Pat. No. 6,489,825 B1 discloses a fast double-edge flip-flop having low power and area consumptions. An inverter, a pair of latches, and a two-to-one multiplexer are thus employed. A first latch outputs a first signal in response to a first data signal when a clock signal is in a first state, and stores the logic state of the first signal when the clock signal is in a second logic state. A second latch outputs a second signal in response to a second data signal when the clock signal is in the second logic state, and stores the logic state of the second signal when the clock signal is in the first logic state. The multiplexer controls the logic state of the flip-flop output signal in response to the logic state of the first signal when the clock signal is in the second logic state, and in response to the logic state of the second signal when the clock signal is in the first logic state.
US patent application US 2004/0041610 A1 discloses a scan design for double-edge triggered flip-flops. The double-edge flip-flop scan cell provides the ability to detect and output data at each edge of a clock signal in a functional mode of an integrated circuit. In a test mode, the double-edge triggered clip-flop scan cell enables test data to be scanned into and out of the scan cell, so as to provide an observability and controllability of the internal state of the scan cell.
U.S. Pat. No. 6,438,023 B1 discloses a double-edge clocked memory device, triggered either by the rising edge, the falling edge or by both edges of a clock signal. Cross-coupled inverters at the inputs are provided to realize short and potentially negative setup times. Cross-coupled tri-state inverters at the outputs improve the clock-to-data times. A pre-charge evaluation method is used to transfer data for storing both at the rising and at the falling edges of the clock signal. Inverters having weak feedback are optionally used to maintain the state of the memory device in the absence of a clock signal.
U.S. Pat. No. 6,400,199 B1 discloses a double-edge triggered difference flip-flop comprising a first difference master circuit, a second difference master circuit, and a difference slave circuit. The first master circuit stores the first input value during the time duration from the leading edge to the trailing edge of the clock. The second master circuit stores the second input value during the time duration from the trailing edge to the leading edge of the clock. The slave circuit is electrically connected to the outputs of the first and second master circuits. The slave circuit comprises a second repeater as the output end of the flip-flop, outputs the first input value at the trailing edge of the clock, and outputs the second input value at the leading edge of the clock.
FIG. 12 shows a typical single-edge triggered D-type flip-flop as is presented in “Halbleiter-Schaltungs-Technik”, U. Tietze, CH. Schenk, page 238, Springer-Verlag, 1989. In principle, the flip-flop is a master-slave structure. A slave latch formed from inverters G21 and G22 is supplied with the data value of a master latch formed from inverters G11, G12, when a clock transition occurs. For example, in the D-type flip-flop depicted in FIG. 12, a data value is sampled by the master latch and, once the clock changes its state, stored into the slave latch and output as a data value Q and/or as an inverted data value, Q. As long as the clock is C=0, the master follows the input signal, and it becomes Q1=D. Meanwhile, the slave stores the old state. When the clock goes to 1, the information D present in this moment is frozen within the master and transferred to the slave and, thus, to the Q output. The information present at the D input at the positive clock edge is thus currently transferred to the Q output. During the remaining time, the state of the D input is without influence. Unlike a JK flip-flop comprising entry blocking, the value read in does not appear as late as at the negative clock edge at the output, but appears immediately. Thus, an advantage of this circuit is the fact that now the entire clock period duration is available for forming the new D signals. When using JK flip-flops, this process must be performed while the clock is 0, i.e. within half the time at a symmetrical clock.
Generally, different characteristic quantities exist with such flip-flops. The time of “CLK2Q” indicates the amount of time one has to wait, starting from a clock event, i.e., for example, from rising or falling clock edges, until that data value which at the time of the clock event was present at the input, appears on the output side.
Thus, it is absolutely necessary to take care, with the flip-flop depicted in FIG. 12, that the slave flip-flop is not opened before the master flip-flop has neatly closed. On the other hand, the master flip-flop must be opened for a sufficiently long time so that the data value at the D input is neatly stored in the master flip-flop. Eventually, the slave flip-flop must be opened for a sufficiently long time so that the data value taken over by the master latch is neatly read into the slave latch.
All these processes, i.e. storing a data value into the master latch, transferring the data value from the master latch to the slave latch, and the data value being fully taken over by the slave latch, must occur within a single clock cycle.
To ensure all these time periods for specific temperature states of a circuit and other external circumstances occurring in the operation of a circuit, so as to prevent any calculation errors from occurring, safety margins are envisaged which are all at the expense of the clock frequency. On the other hand, the clock frequency is responsible for a processor being operated fast. In addition, the power consumption is also associated with the clock frequency. If the clock frequency is higher, i.e. if a larger number of switching transitions occur, the power consumption will also be higher, whereas the power consumption becomes lower when the clock frequency is reduced.
Within a typical logic circuit, many flip-flops exist in many locations. All of these flip-flops must be supplied with a clock, which is provided to the individual flip-flops via a so-called clock tree. This clock tree by now contributes to the current consumption of a circuit at a quite considerable percentage. Therefore, one will strive to have double-edge triggered flip-flops, since the clock frequency may be reduced by half in comparison with single-edge triggered flip-flops. On the other hand, sufficient safety margins must nevertheless be maintained for the individual data transitions within the flip-flop, particularly large safety margins being necessary specifically for correctly reading in a data value into a latch, since a calculation error will occur if the reading-in of a data value into a latch is not ensured.
However, these margins result in that lower clock frequencies can be employed. What is also problematic about these margins is the fact that they will not actually be exhausted for a typical normal operation, but that because of these margins, i.e. for safety reasons, the clock frequency cannot be ramped up to the extent that would actually be desired.